In many present day wireless communication applications, a digital synthesizer is used and often implemented by way of a digital phase locked loop (DPLL) that is used to control a digitally controlled oscillator (DCO) to generate (often referred to as ‘synthesize’) an output radio frequency (local oscillator) signal. Such digital synthesizers provide a benefit of being able to simplify the integration of the synthesizer circuitry within large scale integrated digital circuit devices, as compared with equivalent analogue synthesizers, thereby reducing size, cost, power consumption and design complexity. Furthermore, DPLLs intrinsically present lower phase noise than their analogue counterparts.
All-digital phase locked loops (ADPLLs) can be used as a frequency synthesizer in radio frequency circuits to create a stable local oscillator for transmitters or receivers, due to their low power consumption and high integration level. They can also be used to generate the frequency-modulated continuous wave (FMCW) waveforms required by a radar transmitter.
In a DPLL, data has to be transmitted from a DCO domain to a reference clock domain, preferably without synchronization loss within the loop of the DPLL. As the two domains are asynchronous, the inventors have recognized and appreciated that there is a need to build a mechanism to avoid any (asynchronous clock) metastability region. Metastability occurs when the order of arrival of clock edges is random, e.g. when two clocks are ‘almost’ edge-to-edge synchronous, but where an edge can therefore be lost. Any small jitter (variable delay) then causes the edges to be in reverse order, from one edge of a clock to the next, which causes un-predictable behavior. In a DPLL circuit, such metastability problems sometimes appear as a re-timing effect between a DCO output clock and a reference clock, which may cause errors on the Time-to-Digital Converter (TDC) output, and thereby generate spurs on the DCO output. The re-timing effect is caused due to the fact that the DCO clock is not synchronized with the reference clock. Known mechanisms to deal with the metastability region suffer from component tolerance variation due to, say, Process, Voltage, Temperature (PVT) effects.
U.S. Pat. No. 8,155,256 B2 describes a mechanism that hopes to find the optimal edge from a series of delays, to use in a re-timer circuit. However, the algorithm in U.S. Pat. No. 8,155,256 B2 selects a fixed choice of one delayed output of a TDC output that is used in a re-timer context to decide if CKV or CKVZ (i.e. inverted clock) signal should be used. Such a fixed clock decision and usage thereof has been found to be unable to work over typical, practical, PVT variations.
Accordingly, it is important to generate modulation signals for FMCW in a DPLL that is more insensitive to component tolerances, such as PVT, particularly for example in a re-timer operation.